@INPROCEEDINGS{Grund09a,
  author = {Daniel Grund and Jan Reineke and Gernot Gebhard},
  title = {Branch Target Buffers: {WCET} Analysis and Timing Predictability},
  booktitle = {15th International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2009},
  year = {2009},
  month = {August},
  subproject={R2},
  access={restricted},
  bibtex={grund.rtcsa09.bib},
  pdf={grund.rtcsa09.pdf},
  abstract={One step in the verification of hard real-time
systems is to determine upper bounds on the worst-case
execution times (WCET) of tasks. To obtain tight bounds, a
WCET analysis has to consider microarchitectural features like
caches, branch prediction, and branch target buffers (BTB).
We propose a modular WCET analysis framework for
branch target buffers (BTB), which allows for easy adaptability
to different BTBs. As an example, we investigate the
MOTOROLA POWERPC 56X family (MPC56X), which is used
in automotive and avionic systems. On a set of avionic and
compiler benchmarks, our analysis improves WCET bounds
on average by 13% over no BTB analysis.
Capitalizing on the modularity of our framework, we explore
alternative hardware designs. We propose more predictable
designs, which improve obtainable WCET bounds by up to
20%, reduce analysis time considerably, and simplify the
analysis. We generalize our findings and give advice concerning
hardware used in real-time systems.},
}