VHDL Timing Model Derivation Toolset





Real-time analysis methods for hardware architectures


The VHDL Timing Model Derivation Toolset is a set of tools to support the semi-automatic derivation of timing models used in the aiT timing analysis framework. Within the tool set, Vhdl2Crl2  is able to read in a VHDL description and converts it into an intermediate format called Crl2. Based on that, the model can be examine and explored with the slicer (VhdlSlicer). This effectively supports model understanding. The remaining tools in the tool set can be used to reduce the model to those parts that actually determine the timing behavior of the specified hardware component. In addition, the introduction of model state abstractions is supported. The resulting abstract timing model can be feed to the VhdlPipelineAnalyzerGenerator in order to generate a so called pipeline analysis that fits into the tool chain of the aiT framework.


M. Schlickling and M. Pister. Semi-automatic derivation of timing models for WCET analysis. In Jaejin Lee and Bruce R. Childers, editors, Proceedings of the 2010 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems, pages 67-76, April 2010.

M.A. Maksoud, M. Pister, and M. Schlickling. An abstraction-aware compiler for VHDL models. In International Conference on Computer Engineering and Systems (ICCES '09), pages 3-9, 2009.

M. Schlickling and M. Pister. A framework for static analysis of VHDL code. In 7th International Workshop on Worst-Case Execution Time (WCET) Analysis, 2007.








Proof of Concept